The present invention relates to a pattern inspecting method and a system for use in such a method in which an image or a waveform representing the physical properties of an object such as a semiconductor wafer or the like is obtained by utilizing light, an electron beam or the like, and the image or the waveform is compared with the design information or the resultant image, thereby inspecting a pattern, and a semiconductor wafer manufacturing method employing the same.
As for the conventional method of inspecting a pattern, as described in JP-A-6-294750, there is well known a first method wherein by utilizing the property in which it can be expected that the chips adjacent to one another have the same pattern, a pattern of one chip is compared with that of the chip adjacent thereto, and if there is any difference therebetween, then it is judged that the pattern of any one of the chips has a defect. In addition, as described in JP-A-57-196530, there is well known a second method wherein by utilizing the property in which it can be expected that memory cells within a chip have the same pattern, a pattern of one memory cell is compared with that of the memory cell adjacent thereto, and if there is any difference therebetween, then it is judged that the pattern of any one of the memory cells has a defect.
Further, as described in JP-A-3-232250, there is well known a third method wherein a storage unit for storing therein, on the basis of the pattern arrangement information within a chip, with respect to the scanning direction of a one-dimensional sensor and the storage scanning direction from the starting point of the chip, the data of a chip comparison inspection area and a repeated pattern (a pattern of a memory cell) comparison inspection area is included, and with consideration of both the sensor scanning position and the stage inspection position, it is controlled whether or not the defect output of the chip comparison inspection and the defect output of the repeated pattern comparison inspection can be outputted.
In the conventional first method, two kinds of errors are mixed since the chips have the different patterns as the objects of comparison, and even in the case of the normal portion, the difference occurs so that the identification of the defect of interest to the fine defect becomes difficult. The first error is due to the object. Then, the exposure conditions are different between the different chips because the aligner cannot expose the overall surface of the wafer at the same time, or in the CVD system or the like, the overall surface of the wafer can be processed at the same time, but if the comparison distance is long, then the different thicknesses are obtained in the periphery of the wafer especially so that the different patterns are formed. The second error is due to the inspection system. Then, while the patterns are detected and compared with one another after a predetermined lapse of time because it is difficult to detect a large area at the same time, if the time interval is long, then the detection and comparison are readily to be affected by system drift, vibration and the like. Therefore, in order to ensure the reliability, the system construction will be complicated to increase the cost.
In the conventional second or third method, the pattern of the object to be compared is necessarily present. In other words, the inspection area is limited on the division line between the memories having the comparison direction matching that of the inside of the memory mat portion in which the memory cells are regularly arranged, and also the specification of the area needs to be strictly carried out. In particular, in the recent pattern layout in which the inside of the memory mat is finely divided, the inspection areas need to be set in only the inside of the areas which are obtained by the division. As a result, it will be expected that the area setting takes a lot of time and hence the inspection possible area is limited.